1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming conductive contacts for semiconductor devices using a local interconnect processing scheme.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. Field effect transistors are typically either NFET devices or PFET devices. During the fabrication of complex integrated circuits, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, referred to as a channel region, disposed between the highly doped source/drain regions. The channel length of a transistor is generally considered to be the lateral distance between the source/drain regions. As device dimensions have continued to shrink over recent years, it is becoming more challenging to accurately and repeatedly manufacture integrated circuit products that meet performance criteria established for such integrated circuit products.
FIGS. 1A-1B schematically depict various portions and features of an illustrative prior art device 10. As shown therein, a plurality of spaced apart active regions 12P and 12N are defined in a semiconducting substrate by one or more isolation structures 16. A plurality of PFET devices 20P1-3 are formed in and above the active region 12P and a plurality of NFET devices 22N1-3 are formed in and above the active region 12N. The PFET devices comprise P-doped source/drain regions 20S/D while the NFET devices comprise N-doped source/drain regions 22S/D. In the depicted example, the various PFET and NFET devices share a common electrode structure 30 that extends across the separated active regions 12P, 12N and the isolation region 16 therebetween. For example, PFET transistor 20P1 and NFET transistor 22N1 share a common gate electrode structure 30 that extends across both of the active regions 12P, 12N and the isolation region 16 between those two active regions.
Still with continuing reference to FIGS. 1A-1B, the device 10 further comprises a plurality of source/drain contacts 24 that are conductively coupled to the source/drain regions of the various transistors. The device level contacts 24 may also be referred to as “trench silicide” regions within the industry. The device level contacts 24 are positioned in a layer of insulating material, which is not shown in FIGS. 1A-1B to facilitate explanation. At least one of the device level contacts 24 serves as a local interconnect structure 26 that spans across the isolation region 16 and conductively couples source/drain regions on the two isolated active regions 12P, 12N. An illustrative gate contact 28 that is conductively coupled to one of the gate structures 30 is also depicted in FIGS. 1A-1B.
With each new technology generation, virtually all dimensions of various features of an integrated circuit product are typically reduced. For example, as device dimensions are reduced, the lateral spacing 32 between the gate contact 28 and the local interconnect structure 26 had decreased. In some cases, the lateral spacing 32 may be as little as about 10 nm. As this lateral spacing decreases, there is an increased risk of creating short circuits. Of course, one way to rectify this problem would be to simply increase the spacing between adjacent transistors. However, such an approach would be very costly in terms of the plot space on the device that is lost and would run counter to the trend in integrated circuit products of reducing the size of such products.
The present disclosure is directed to various methods of forming conductive contacts for semiconductor devices using a local interconnect processing scheme that may avoid, or at least reduce, the effects of one or more of the problems identified above.